SoC Design + Verification RLVR Diagnostic Sample: 5 Tasks
A diagnostic package spanning UART, memory, and RV32 CPU work. It contains three RTL design or repair tasks and two verification-authoring tasks built around Verilog/SystemVerilog, Python, cocotb, Icarus Verilog, Verilator, and Yosys.
Included
- Five task bundles with specifications, editable starter files, Makefiles, and public tests
- Task metadata, locked reward contracts, environment requirements, provenance, and admission summaries
- Protocol and trajectory schemas, aggregate evaluation results, and sanitized per-snapshot reward trajectories from one fresh attempt per task
- A SHA-256 manifest covering the delivered files
- Artifact version 1.0.2, delivered as
soc-dv-gpt-5.3-codex-spark-customer-package-v1.0.2.zip
Not included
- Private graders, hidden tests, mutation banks, gold solutions, or completed model solutions
- Raw agent messages, candidate diffs, provider thread or receipt identifiers, credentials, or private toolchain images
- A turnkey hidden-reward runtime or permission to represent the evaluation results as a production benchmark
The sample includes third-party source material. Applicable third-party terms and notices govern the corresponding files. The sample license governs operator-authored packaging, curation, metadata, schemas, verification contracts, and diagnostic evidence without reducing rights provided by those terms.
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