RTL Tasks

We offer a massive corpus and RL environment for synthesizing and simulating VHDL, Verilog, and SystemVerilog.

Training AI on chip design

Pre-training
  • Curated RTL corpus: Verilog, VHDL, and SystemVerilog organized for language model pre-training on hardware design
  • Full project context: Not just isolated modules, but complete designs with testbenches, constraints, Makefiles, and documentation
  • Architecture diversity: Processors, accelerators, interconnects, memory controllers, and peripherals spanning every major chip category
  • EDA tool flows: Synthesis scripts, OpenROAD/Yosys/OpenLane configurations, and physical design collateral

Post-training (RL Environments)
  • Open-source reward verification: Verilator, Yosys, cocotb, Icarus Verilog, GHDL, GTKWave, OpenROAD, and OpenLane compile, simulate, synthesize, inspect waveforms, and measure implementation results so rewards are grounded in executable hardware behavior
  • Custom UVM trajectory ports: Purpose-built UVM ports replay and verify full SystemVerilog trajectories, including intermediate edits, assertions, testbench interactions, coverage, and final RTL, across the entire codebase
  • Multi-signal reward gates: Functional correctness, compilation, simulation, synthesis, area, power, timing, coverage, and waveform agreement produce deterministic pass/fail and graded rewards
  • Evaluation and reference circuits: Reference designs and known-good implementations for evaluating generated RTL quality

RTL by Chip Type

AI & Accelerators

TPU
  • Systolic arrays: Weight-stationary, output-stationary, and row-stationary dataflows for matrix multiplication in training and inference silicon
  • Tensor processing pipelines: Activation functions, accumulator chains, and configurable NxN matrix multiply units
  • AI accelerator SoCs: End-to-end TPU-style designs with on-chip SRAM, DMA engines, and host interfaces

GPU
  • Shader cores & SIMD pipelines: Warp schedulers, register files, and execution units for GPGPU compute
  • Tensor & matrix cores: Dedicated FP16/INT8 matrix multiply units for deep learning workloads
  • 2D/3D graphics engines: Rasterizers, framebuffer controllers, display pipelines, and video processing

NPU
  • CNN accelerators: Convolutional neural network engines with configurable kernel sizes, pooling, and activation layers
  • Neural network processors: Spiking neural networks, MLP accelerators, and on-chip inference engines
  • Edge ML hardware: Low-power neural engines for always-on inference, keyword spotting, and image classification

DPU
  • Xilinx DPU inference engines: DPUCZDX8G and variant configurations for CNN inference on Zynq and ZCU platforms
  • Data processing units: DAG processing architectures, dual-clock domain processing, and memory pool controllers
  • Network-attached processing: SmartNIC-style offload engines for packet parsing, classification, and transformation

Processors & Systems

CPU
  • RISC-V cores: Single-cycle through superscalar out-of-order implementations, privilege modes, and ISA extensions
  • ARM Cortex & custom ARM: Pipelined and multi-cycle ARM processors with SoC integration logic
  • MIPS architectures: Classic 5-stage pipelines, multi-cycle designs, and full ISA implementations
  • Custom ISA processors: 8-bit through 64-bit CPU designs, ALUs, branch predictors, and cache hierarchies
  • VLIW processors: Very Long Instruction Word architectures with multi-issue execution units, instruction bundling, and static scheduling

MPU
  • 8-bit & 16-bit microprocessors: 8051, 6502, PIC, and AVR-compatible implementations in Verilog and VHDL
  • 32-bit microcontrollers: ARM Cortex-M0 based SoCs, OpenMSP430 designs, and embedded processor cores
  • Microcomputer systems: Complete microprocessor designs with peripherals, memory controllers, and bus interfaces

MCU
  • 8051 & legacy cores: Classic 8051 implementations, turbo variants, and embedded cryptosystem integrations in Verilog and VHDL
  • RISC-V & ARM Cortex-M MCUs: Soft microcontroller SoCs with APB/AHB buses, GPIO, UART, SPI, I2C, timers, and interrupt controllers
  • Peripheral & IO subsystems: Standalone UART, SPI, I2C, GPIO, watchdog, and PWM timer IP blocks for embedded integration

SoC
  • Complete system-on-chip designs: Integrated CPU, memory, interconnect, peripheral, and accelerator subsystems in Verilog, VHDL, and SystemVerilog
  • Bus fabrics & interconnects: AXI, AHB, APB, Wishbone, NoC, crossbar, arbitration, and bridge logic for multi-IP integration
  • Platform peripherals: UART, SPI, I2C, GPIO, timers, interrupt controllers, DMA engines, boot ROMs, and memory-mapped control blocks

Memory

DRAM
  • DDR & LPDDR controllers: Command scheduling, bank management, refresh, burst handling, and AXI integration across modern memory interfaces
  • SDRAM subsystems: Row activation, precharge, arbitration, timing enforcement, and initialization logic
  • PHY-facing logic: DFI interfaces, calibration control, read and write training, and error reporting

SRAM
  • Single-port & dual-port memories: Synthesizable synchronous SRAMs with configurable widths, depths, byte enables, and read modes
  • Cache & scratchpad arrays: Banked data and tag memories, local accelerator storage, and multi-client arbitration
  • Reliability features: ECC, parity, scrubbing, memory BIST, and fault-injection logic

Flash & Non-Volatile Memory
  • NOR & NAND flash controllers: Command sequencing, page and block operations, buffering, ECC, and bad-block management
  • EEPROM & ROM subsystems: Memory-mapped interfaces, boot storage, initialization, and access-control logic
  • Emerging memory controllers: Protocol and control logic for MRAM, FRAM, and ReRAM-based systems

Specialized Memory
  • HBM subsystems: Multi-channel scheduling, pseudo-channel control, high-bandwidth interconnects, and traffic arbitration
  • CAM & TCAM: Associative lookup, masked matching, priority encoding, and table update logic
  • FIFO & buffer memories: Synchronous and asynchronous FIFOs, clock-domain crossing, packet buffers, and streaming queues

Implementation Platforms

ASIC
  • Complete ASIC flows: RTL-to-GDSII designs including synthesis, place-and-route, and signoff for tapeout
  • Standard cell & physical design: Cell libraries, floorplanning, power grid synthesis, and timing closure at advanced nodes
  • Application-specific designs: Custom cryptographic engines, DSP blocks, communication controllers, and sensor interfaces

FPGA
  • Xilinx & Intel/Altera platforms: Vivado and Quartus project files, IP integrations, and board-level designs across device families
  • FPGA-based accelerators: CNN inference, cryptomining, signal processing, and high-speed data acquisition on reconfigurable fabric
  • Prototyping & IP cores: Reusable FPGA IP for Ethernet, USB, HDMI, SDRAM, SPI, I2C, UART, and PCIe interfaces

Countless more architectures available on request.

FAQ

Where is the data from?

Our packages combine licensed third-party RTL with operator-authored task adaptations, synthetic transformations, verification assets, evaluation metadata, diagnostic evidence, and curation. Applicable open-source rights and notices remain intact; proprietary claims apply only to operator-authored materials and the curated compilation. Every RLVR task is validated with EDA tools through compilation, simulation, and synthesis checks before it is included.

What do your licenses cover?

Exclusive and non-exclusive licenses cover our compiled dataset packages, verification artifacts, manifests, and curation methodology, not third-party rights.

Who owns trained models and outputs?

You retain ownership of the trained models and outputs you create using our data.

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Contact us via:
Email: root@puul.ai
Signal/text: 650-880-9229