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SoC Design + Verification RLVR Diagnostic Sample: 5 Tasks

A diagnostic package spanning UART, memory, and RV32 CPU work. It contains three RTL design or repair tasks and two verification-authoring tasks built around Verilog/SystemVerilog, Python, cocotb, Icarus Verilog, Verilator, and Yosys.

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The sample includes third-party source material. Applicable third-party terms and notices govern the corresponding files. The sample license governs operator-authored packaging, curation, metadata, schemas, verification contracts, and diagnostic evidence without reducing rights provided by those terms.

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